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Disambiguation of "Wen, Xiaoqing"

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CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.

, , , , , , , and . ATS, page 397-402. IEEE Computer Society, (2008)

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Dr. -Ing. Christoph Wenzel University of Stuttgart

Dr. rer. nat. Tim Wendlandt University of Stuttgart

Ingeborg Wenger University of Stuttgart

Florian Wenz University of Stuttgart

Marco Wende University of Stuttgart

 

Other publications of authors with the same name

Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test., , , , and . ATS, page 173-178. IEEE Computer Society, (2016)A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST., , , , and . ATS, page 203-208. IEEE Computer Society, (2016)Fault Diagnosis of Physical Defects Using Unknown Behavior Model., , , and . J. Comput. Sci. Technol., 20 (2): 187-194 (2005)Test Pattern Modification for Average IR-Drop Reduction., , , , and . IEEE Trans. VLSI Syst., 24 (1): 38-49 (2016)A Testable Design of Logic Circuits under Highly Observable Condition., and . IEEE Trans. Computers, 41 (5): 654-659 (1992)Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (3): 499-512 (2016)On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST., , , , , , and . Asian Test Symposium, page 19-24. IEEE Computer Society, (2013)Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling., , , , , , , , , and 1 other author(s). Asian Test Symposium, page 90-95. IEEE Computer Society, (2011)Towards the next generation of low-power test technologies.. ASICON, page 232-235. IEEE, (2011)VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG., , , , , , and . IEEE Design & Test of Computers, 25 (2): 122-130 (2008)