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Disambiguation of "Wang, Laung-Terng"

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On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression.

, , , , , and . VLSI Design, page 279-284. IEEE Computer Society, (2013)

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Dr. rer. nat. Lei Wang University of Stuttgart

Zhe Wang University of Stuttgart

Dr. Dongren Wang University of Stuttgart

Xiwei Wang University of Stuttgart

FangFang Wang University of Stuttgart

 

Other publications of authors with the same name

Test compression and logic BIST at your fingertips., , , , and . ITC, page 2. IEEE Computer Society, (2005)A circular pipeline processing based deterministic parallel test pattern generator., , , and . ITC, page 1-8. IEEE Computer Society, (2013)Logic BIST Architecture for System-Level Test and Diagnosis., , , , , , , , , and 5 other author(s). Asian Test Symposium, page 21-26. IEEE Computer Society, (2009)VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG., , , , , , and . IEEE Design & Test of Computers, 25 (2): 122-130 (2008)Testing of Synchronizers in Asynchronous FIFO., , , and . J. Electronic Testing, 29 (1): 49-72 (2013)Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing., , , , , , and . J. Electronic Testing, 24 (4): 379-391 (2008)Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (3): 455-463 (2011)Circuits for pseudoexhaustive test pattern generation., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 7 (10): 1068-1080 (1988)On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST., , , , , , and . Asian Test Symposium, page 19-24. IEEE Computer Society, (2013)CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator., , and . J. Electronic Testing, 32 (5): 625-638 (2016)