PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Yotsuyanagi, Hiroyuki"

Author of the publication

copydeleteadd this publication to your clipboard
Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement.

, , and . IEICE Transactions, 78-D (7): 861-867 (1995)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Yotsuyanagi, Hiroyuki
add a person with the name Yotsuyanagi, Hiroyuki
 

Other publications of authors with the same name

Testability Analysis of IDDQ Testing with Large Threshold Value., , , and . DFT, page 367-375. IEEE Computer Society, (2000)Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture., , and . 3DIC, page 1-6. IEEE, (2011)Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States., , , and . Asian Test Symposium, page 23-. IEEE Computer Society, (2001)Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field., , , , and . DELTA, page 387-391. IEEE Computer Society, (2002)A supply current testable register string DAC of decoder type., , , and . ISCIT, page 58-63. IEEE, (2011)Electric field for detecting open leads in CMOS logic circuits by supply current testing., , , and . ISCAS (3), page 2995-2998. IEEE, (2005)Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees., , , , and . J. Electronic Testing, 21 (6): 613-620 (2005)High speed IDDQ test and its testability for process variation., , , , and . Asian Test Symposium, page 344-349. IEEE Computer Society, (2000)A built-in supply current test circuit for electrical interconnect tests of 3D ICs., , , and . 3DIC, page 1-6. IEEE, (2014)Synthesis for Testability by Sequential Redundancy Removal Using Retiming., , and . FTCS, page 33-40. IEEE Computer Society, (1995)