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Impact of resistive-open defects on the heat current of TAS-MRAM architectures., , , , , , , , and . DATE, page 532-537. IEEE, (2012)A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction., , , , , , , , and . European Test Symposium, page 81-86. IEEE Computer Society, (2010)Random Adjacent Sequences: An Efficient Solution for Logic BIST., , , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 413-424. Kluwer, (2001)Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization., , , , and . European Test Symposium, page 116-121. IEEE Computer Society, (2005)Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes., , , , , , and . European Test Symposium, page 132-137. IEEE Computer Society, (2010)Defect analysis in power mode control logic of low-power SRAMs., , , , , , and . European Test Symposium, page 1. IEEE Computer Society, (2012)Through-Silicon-Via resistive-open defect analysis., , , , , and . European Test Symposium, page 1. IEEE Computer Society, (2012)Low-power SRAMs power mode control logic: Failure analysis and test solutions., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation., , , , and . IEEE Trans. VLSI Syst., 21 (5): 958-970 (2013)Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test., , , , , and . J. Electronic Testing, 21 (2): 169-179 (2005)