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Patrick Kopper University of Stuttgart

GALÆXI Scaling, , , , , , , , und . Dataset, (2024)Related to: Kempf, Daniel et al. “GALÆXI: Solving complex compressible flows with high-order discontinuous Galerkin methods on accelerator-based systems.” (2024). arXiv: 2404.12703.
GALÆXI Scaling, , , , , , , , und . Dataset, (2024)Related to: Kempf, Daniel et al. “GALÆXI: Solving complex compressible flows with high-order discontinuous Galerkin methods on accelerator-based systems.” (2024). arXiv: 2404.12703.GALÆXI Validation: Taylor-Green Vortex, , , , , , , , und . Dataset, (2024)Related to: Kempf, Daniel et al. “GALÆXI: Solving complex compressible flows with high-order discontinuous Galerkin methods on accelerator-based systems.” (2024). arXiv: 2404.12703.GALÆXI Verification: Convergence Tests, , , , , , , , und . Dataset, (2024)Related to: Kempf, Daniel et al. “GALÆXI: Solving complex compressible flows with high-order discontinuous Galerkin methods on accelerator-based systems.” (2024). arXiv: 2404.12703.
 

Weitere Publikationen von Autoren mit dem selben Namen

Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint., , , , und . ITC, Seite 488-493. IEEE Computer Society, (2003)Power Driven Chaining of Flip-Flops in Scan Architectures., , , und . ITC, Seite 796-803. IEEE Computer Society, (2002)Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity., , , , , , , und . ISCAS (1), Seite 110-113. IEEE, (1999)Delay-Fault Diagnosis by Critical-Path Tracing., , und . IEEE Design & Test of Computers, 9 (4): 27-32 (1992)A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk., , und . J. Electronic Testing, 28 (2): 201-214 (2012)Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories., , , , , und . J. Electronic Testing, 21 (5): 551-561 (2005)A Ring Architecture Strategy for BIST Test Pattern Generation., , , und . J. Electronic Testing, 19 (3): 223-231 (2003)A Scan-BIST Structure to Test Delay Faults in Sequential Circuits., , , , und . J. Electronic Testing, 14 (1-2): 95-102 (1999)An advanced diagnostic method for delay faults in combinational faulty circuits., , und . J. Electronic Testing, 6 (3): 277-294 (1995)An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs., , , und . J. Electronic Testing, 22 (2): 161-172 (2006)