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Disambiguation of "Pravossoudovitch, Serge"

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Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.

, , , , , , , and . ISCAS (1), page 110-113. IEEE, (1999)

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Other publications of authors with the same name

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test., , , , , and . J. Electronic Testing, 21 (2): 169-179 (2005)A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction., , , , , , and . J. Electronic Testing, 24 (4): 353-364 (2008)Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles., , , , and . VLSI-SoC, volume 240 of IFIP, page 267-281. Springer, (2005)Failure Analysis and Test Solutions for Low-Power SRAMs., , , , , , , and . Asian Test Symposium, page 459-460. IEEE Computer Society, (2011)Comprehensive bridging fault diagnosis based on the SLAT paradigm., , , , , , , and . DDECS, page 264-269. IEEE Computer Society, (2009)Defect Analysis for Delay-Fault BIST in FPGAs., , , and . IOLTS, page 124-128. IEEE Computer Society, (2003)A new test pattern generation method for delay fault testing., , , , and . VTS, page 296-301. IEEE Computer Society, (1996)Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption., , , and . Asian Test Symposium, page 89-94. IEEE Computer Society, (1999)On Using Efficient Test Sequences for BIST., , , , and . VTS, page 145-152. IEEE Computer Society, (2002)Advanced test methods for SRAMs., , , , and . VTS, page 300-301. IEEE Computer Society, (2012)