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Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.

, , , and . Asian Test Symposium, page 89-94. IEEE Computer Society, (1999)

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A new test pattern generation method for delay fault testing., , , , and . VTS, page 296-301. IEEE Computer Society, (1996)Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption., , , and . Asian Test Symposium, page 89-94. IEEE Computer Society, (1999)On Using Efficient Test Sequences for BIST., , , , and . VTS, page 145-152. IEEE Computer Society, (2002)Advanced test methods for SRAMs., , , , and . VTS, page 300-301. IEEE Computer Society, (2012)Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs., , , , , and . VTS, page 361-368. IEEE Computer Society, (2007)A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction., , , , , , , , and . European Test Symposium, page 81-86. IEEE Computer Society, (2010)Random Adjacent Sequences: An Efficient Solution for Logic BIST., , , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 413-424. Kluwer, (2001)Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization., , , , and . European Test Symposium, page 116-121. IEEE Computer Society, (2005)Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes., , , , , , and . European Test Symposium, page 132-137. IEEE Computer Society, (2010)Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity., , , , , , , and . ISCAS (1), page 110-113. IEEE, (1999)