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IDDQ Test and Diagnosis of CMOS Circuits., and . IEEE Design & Test of Computers, 12 (4): 60-67 (1995)Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (2): 301-312 (2013)Detectability Conditions of Full Opens in the Interconnections., , and . J. Electronic Testing, 17 (2): 85-95 (2001)Digital Signature Proposal for Mixed-Signal Circuits., and . J. Electronic Testing, 17 (5): 385-393 (2001)Full Open Defects in Nanometric CMOS., , , , , and . VTS, page 119-124. IEEE Computer Society, (2008)On estimating bounds of the quiescent current for I/sub DDQ/ testin., and . VTS, page 106-111. IEEE Computer Society, (1996)Power Dissipation During Testing: Should We Worry About it?, , , , , , and . VTS, page 456-457. IEEE Computer Society, (1997)Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations., , and . ED&TC, page 186-194. IEEE Computer Society, (1996)BIST architecture to detect defects in tsvs during pre-bond testing., , and . ETS, page 1. IEEE Computer Society, (2013)IDDQ Characterization in Submicron CMOS., and . ITC, page 136-145. IEEE Computer Society, (1997)