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BiScaled-DNN: Quantizing Long-tailed Datastructures with Two Scale Factors for Deep Neural Networks.

S. Jain, S. Venkataramani, V. Srinivasan, J. Choi, K. Gopalakrishnan, and L. Chang. DAC, page 201. ACM, (2019)

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An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches.L. Chang, R. Montoye, Y. Nakamura, K. Batson, R. Eickemeyer, R. Dennard, W. Haensch, and D. Jamsek. J. Solid-State Circuits, 43 (4): 956-963 (2008)Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs).Y. Lee, D. Kim, J. Cai, I. Lauer, L. Chang, S. Koester, D. Blaauw, and D. Sylvester. IEEE Trans. VLSI Syst., 21 (9): 1632-1643 (2013)A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple.S. Bang, J. sun Seo, I. Lee, S. Jeong, N. Pinckney, D. Blaauw, D. Sylvester, and L. Chang. VLSIC, page 336-. IEEE, (2015)Near-threshold operation for power-efficient computing?: it depends...L. Chang, and W. Haensch. DAC, page 1159-1163. ACM, (2012)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, V. Srinivasan, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation.G. Ditlow, R. Montoye, S. Storino, S. Dance, S. Ehrenreich, B. Fleischer, T. Fox, K. Holmes, J. Mihara, Y. Nakamura and 4 other author(s). ISSCC, page 256-258. IEEE, (2011)A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS.M. Qazi, K. Stawiasz, L. Chang, and A. Chandrakasan. ISSCC, page 350-351. IEEE, (2010)Across the Stack Opportunities for Deep Learning Acceleration.V. Srinivasan, B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). ISLPED, page 35:1-35:2. ACM, (2018)Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions.T. Fischer, B. Nam, L. Chang, T. Kuroda, and M. Pertijs. J. Solid-State Circuits, 49 (1): 4-8 (2014)Session 17 overview: Embedded memory and DRAM I/O: Memory subcommittee.L. Chang, and T. Yoshikawa. ISSCC, page 308-309. IEEE, (2015)

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BiScaled-DNN: Quantizing Long-tailed Datastructures with Two Scale Factors for Deep Neural Networks.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML BiScaled-DNN: Quantizing Long-tailed Datastructures with Two Scale Factors for Deep Neural Networks.

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BiScaled-DNN: Quantizing Long-tailed Datastructures with Two Scale Factors for Deep Neural Networks.