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A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.

B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, V. Srinivasan, J. Choi, S. Mueller, A. Agrawal, T. Babinsky, N. Cao, C. Chen, P. Chuang, T. Fox, G. Gristede, M. Guillorn, H. Haynie, M. Klaiber, D. Lee, S. Lo, G. Maier, M. Scheuermann, S. Venkataramani, C. Vezyrtzis, N. Wang, F. Yee, C. Zhou, P. Lu, B. Curran, L. Chang, and K. Gopalakrishnan. VLSI Circuits, page 35-36. IEEE, (2018)

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Bruno Ohngemach University of Stuttgart

Kathrin Ohmer University of Stuttgart

Sophie Ohnmacht University of Stuttgart

Peter Ohlhausen University of Stuttgart

Other publications of authors with the same name

Intelligent NoC with neuro-fuzzy bandwidth regulation for a 51 IP object recognition processor.S. Lee, J. Oh, M. Kim, J. Park, J. Kwon, J. Kim, and H. Yoo. CICC, page 1-4. IEEE, (2010)A 22.4 mW competitive fuzzy edge detection processor for volume rendering.J. Kwon, M. Kim, J. Oh, and H. Yoo. ISCAS, page 1883-1886. IEEE, (2010)A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.S. Lee, A. Agrawal, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen and 34 other author(s). IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)A 118.4 GB/s Multi-Casting Network-on-Chip With Hierarchical Star-Ring Combined Topology for Real-Time Object Recognition.J. Kim, J. Park, S. Lee, M. Kim, J. Oh, and H. Yoo. J. Solid-State Circuits, 45 (7): 1399-1409 (2010)An attention controlled multi-core architecture for energy efficient object recognition.J. Kim, S. Oh, S. Lee, M. Kim, J. Oh, and H. Yoo. Sig. Proc.: Image Comm., 25 (5): 363-376 (2010)A 345mW heterogeneous many-core processor with an intelligent inference engine for robust object recognition.S. Lee, J. Oh, M. Kim, J. Park, J. Kwon, and H. Yoo. ISSCC, page 332-333. IEEE, (2010)A simultaneous multithreading heterogeneous object recognition processor with machine learning based dynamic resource management.J. Oh, G. Kim, J. Park, I. Hong, S. Lee, J. Kim, and H. Yoo. COOL Chips, page 1-3. IEEE Computer Society, (2012)A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management.J. Kim, S. Lee, J. Oh, M. Kim, and H. Yoo. ISLPED, page 365-370. ACM, (2009)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, V. Srinivasan, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)A 92-mW Real-Time Traffic Sign Recognition System With Robust Illumination Adaptation and Support Vector Machine.J. Park, J. Kwon, J. Oh, S. Lee, J. Kim, and H. Yoo. J. Solid-State Circuits, 47 (11): 2711-2723 (2012)

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Disambiguation of "Oh, Jinwook"

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A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.

Please choose a person to relate this publication to

Bruno Ohngemach University of Stuttgart

Kathrin Ohmer University of Stuttgart

Sophie Ohnmacht University of Stuttgart

Peter Ohlhausen University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Oh, Jinwook"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.

Please choose a person to relate this publication to

Bruno Ohngemach University of Stuttgart

Kathrin Ohmer University of Stuttgart

Sophie Ohnmacht University of Stuttgart

Peter Ohlhausen University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.