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A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference., , , , , , , , , and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)An innovative low-power high-performance programmable signal processor for digital communications., , , , , , , , , and 6 other author(s). IBM Journal of Research and Development, 47 (2-3): 299-326 (2003)Efficient AI System Design With Cross-Layer Approximate Computing., , , , , , , , , and 30 other author(s). Proc. IEEE, 108 (12): 2232-2250 (2020)A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation., , , , , , , , , and 4 other author(s). ISSCC, page 256-258. IEEE, (2011)The IBM Blue Gene/Q Compute Chip., , , , , , , , , and 5 other author(s). IEEE Micro, 32 (2): 48-60 (2012)Across the Stack Opportunities for Deep Learning Acceleration., , , , , , , , , and 21 other author(s). ISLPED, page 35:1-35:2. ACM, (2018)Active Memory Cube: A processing-in-memory architecture for exascale systems., , , , , , , , , and 22 other author(s). IBM Journal of Research and Development, (2015)Design methodology for semi custom processor cores., , , , , and . ACM Great Lakes Symposium on VLSI, page 448-452. ACM, (2004)