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An innovative low-power high-performance programmable signal processor for digital communications.

, , , , , , , , , , , , , , , and . IBM Journal of Research and Development, 47 (2-3): 299-326 (2003)

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CARS: A New Code Generation Framework for Clustered ILP Processors., , and . HPCA, page 133-143. IEEE Computer Society, (2001)A Register File Architecture and Compilation Scheme for Clustered ILP Processors., , and . Euro-Par, volume 2400 of Lecture Notes in Computer Science, page 500-511. Springer, (2002)3D stacking of high-performance processors., , , , , , , , and . HPCA, page 500-511. IEEE Computer Society, (2014)An innovative low-power high-performance programmable signal processor for digital communications., , , , , , , , , and 6 other author(s). IBM Journal of Research and Development, 47 (2-3): 299-326 (2003)An eight-issue tree-VLIW processor for dynamic binary translation., , , , , , and . ICCD, page 488-495. (1998)Formal verification of correctness and performance of random priority-based arbiters., , and . FMCAD, page 101-107. IEEE, (2009)Data Hiding in Compiled Program Binaries for Enhancing Computer System Performance., , , and . Information Hiding, volume 3727 of Lecture Notes in Computer Science, page 357-371. Springer, (2005)Research From the IEEE IBM AI Compute and Emerging Technology Symposia., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 9 (3): 435-438 (2019)