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Disambiguation of "Chang, Leland"

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A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple.

, , , , , , , and . VLSIC, page 336-. IEEE, (2015)

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Other publications of authors with the same name

Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs)., , , , , , , and . IEEE Trans. VLSI Syst., 21 (9): 1632-1643 (2013)An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches., , , , , , , and . J. Solid-State Circuits, 43 (4): 956-963 (2008)A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple., , , , , , , and . VLSIC, page 336-. IEEE, (2015)Near-threshold operation for power-efficient computing?: it depends..., and . DAC, page 1159-1163. ACM, (2012)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference., , , , , , , , , and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS., , , and . ISSCC, page 350-351. IEEE, (2010)A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation., , , , , , , , , and 4 other author(s). ISSCC, page 256-258. IEEE, (2011)Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions., , , , and . J. Solid-State Circuits, 49 (1): 4-8 (2014)Across the Stack Opportunities for Deep Learning Acceleration., , , , , , , , , and 21 other author(s). ISLPED, page 35:1-35:2. ACM, (2018)A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS., , , and . J. Solid-State Circuits, 46 (1): 85-96 (2011)