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A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 51 (2): 557-567 (2016)Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC., , , , , , , , , and 4 other author(s). ESSCIRC, page 269-272. IEEE, (2016)Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET., , , , , , and . CICC, page 1-4. IEEE, (2019)A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm., , , , , , , , , and 7 other author(s). VLSI Circuits, page 300-. IEEE, (2019)Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference., , , , , , , , and . DAC, page 81. ACM, (2019)A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 55 (4): 920-932 (2020)A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI., , , , , , , , , and 9 other author(s). J. Solid-State Circuits, 51 (4): 930-942 (2016)Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM., , , , , and . ESSDERC, page 98-101. IEEE, (2014)A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI., , , , , , , , , and 9 other author(s). VLSIC, page 316-. IEEE, (2015)A modular digital VLSI flow for high-productivity SoC design., , , , , , , , , and 5 other author(s). DAC, page 72:1-72:6. ACM, (2018)