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A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.

B. Zimmer, R. Venkatesan, Y. Shao, J. Clemons, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina, S. Tell, Y. Zhang, W. Dally, J. Emer, C. Gray, S. Keckler, and B. Khailany. VLSI Circuits, page 300-. IEEE, (2019)

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Reading spin-torque memory with spin-torque sensors.M. Sharad, R. Venkatesan, X. Fong, A. Raghunathan, and K. Roy. NANOARCH, page 40-41. IEEE Computer Society, (2013)DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes.R. Venkatesan, M. Sharad, K. Roy, and A. Raghunathan. DATE, page 1825-1830. EDA Consortium San Jose, CA, USA / ACM DL, (2013)VESPA: Variability emulation for System-on-Chip performance analysis.V. Kozhikkottu, R. Venkatesan, A. Raghunathan, and S. Dey. DATE, page 2-7. IEEE, (2011)SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing.S. Ramasubramanian, R. Venkatesan, M. Sharad, K. Roy, and A. Raghunathan. ISLPED, page 15-20. ACM, (2014)Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches.M. Sharad, R. Venkatesan, A. Raghunathan, and K. Roy. ISLPED, page 64-69. IEEE, (2013)Emulation-Based Analysis of System-on-Chip Performance Under Variations.V. Kozhikkottu, R. Venkatesan, A. Raghunathan, and S. Dey. IEEE Trans. VLSI Syst., 24 (12): 3401-3414 (2016)TapeCache: a high density, energy efficient cache based on domain wall memory.R. Venkatesan, V. Kozhikkottu, C. Augustine, A. Raychowdhury, K. Roy, and A. Raghunathan. ISLPED, page 185-190. ACM, (2012)Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage.R. Venkatesan, M. Sharad, K. Roy, and A. Raghunathan. JETC, 12 (1): 4:1-4:27 (2015)A modular digital VLSI flow for high-productivity SoC design.B. Khailany, E. Khmer, R. Venkatesan, J. Clemons, J. Emer, M. Fojtik, A. Klinefelter, M. Pellauer, N. Pinckney, Y. Shao and 5 other author(s). DAC, page 72:1-72:6. ACM, (2018)MACACO: Modeling and analysis of circuits for approximate computing.R. Venkatesan, A. Agarwal, K. Roy, and A. Raghunathan. ICCAD, page 667-673. IEEE Computer Society, (2011)

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A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.

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A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.