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A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.

B. Zimmer, R. Venkatesan, Y. Shao, J. Clemons, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina, S. Tell, Y. Zhang, W. Dally, J. Emer, C. Gray, S. Keckler, and B. Khailany. VLSI Circuits, page 300-. IEEE, (2019)

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Jason Kennedy Appelbaum University of Stuttgart

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EVA: An efficient vision architecture for mobile systems.J. Clemons, A. Pellegrini, S. Savarese, and T. Austin. CASES, page 13:1-13:10. IEEE, (2013)MEVBench: A mobile computer vision benchmarking suite.J. Clemons, H. Zhu, S. Savarese, and T. Austin. IISWC, page 91-102. IEEE Computer Society, (2011)vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design.M. Rhu, N. Gimelshein, J. Clemons, A. Zulfiqar, and S. Keckler. MICRO, page 1-13. IEEE Computer Society, (2016)GA3C: GPU-based A3C for Deep Reinforcement Learning.M. Babaeizadeh, I. Frosio, S. Tyree, J. Clemons, and J. Kautz. CoRR, (2016)Structurally Sparsified Backward Propagation for Faster Long Short-Term Memory Training.M. Zhu, J. Clemons, J. Pool, M. Rhu, S. Keckler, and Y. Xie. CoRR, (2018)EFFEX: an embedded processor for computer vision based feature extraction.J. Clemons, A. Jones, R. Perricone, S. Savarese, and T. Austin. DAC, page 1020-1025. ACM, (2011)MVSS: Michigan Visual Sonification System.J. Clemons, S. Bao, S. Savarese, T. Austin, and V. Sharma. ESPA, page 143-146. IEEE, (2012)A modular digital VLSI flow for high-productivity SoC design.B. Khailany, E. Khmer, R. Venkatesan, J. Clemons, J. Emer, M. Fojtik, A. Klinefelter, M. Pellauer, N. Pinckney, Y. Shao and 5 other author(s). DAC, page 72:1-72:6. ACM, (2018)A patch memory system for image processing and computer vision.J. Clemons, C. Cheng, I. Frosio, D. Johnson, and S. Keckler. MICRO, page 1-13. IEEE Computer Society, (2016)A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.B. Zimmer, R. Venkatesan, Y. Shao, J. Clemons, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina and 7 other author(s). VLSI Circuits, page 300-. IEEE, (2019)

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Disambiguation of "Clemons, Jason"

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A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.

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Jason Kennedy Appelbaum University of Stuttgart

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PUMA

Disambiguation of "Clemons, Jason"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.

Please choose a person to relate this publication to

Jason Kennedy Appelbaum University of Stuttgart

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Disambiguation

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A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.