%0 Conference Paper %1 conf/vlsic/ZimmerVSCFJKKPR19 %A Zimmer, Brian %A Venkatesan, Rangharajan %A Shao, Yakun Sophia %A Clemons, Jason %A Fojtik, Matthew %A Jiang, Nan %A Keller, Ben %A Klinefelter, Alicia %A Pinckney, Nathaniel Ross %A Raina, Priyanka %A Tell, Stephen G. %A Zhang, Yanqing %A Dally, William J. %A Emer, Joel S. %A Gray, C. Thomas %A Keckler, Stephen W. %A Khailany, Brucek %B VLSI Circuits %D 2019 %I IEEE %K dblp %P 300- %T A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2019.html#ZimmerVSCFJKKPR19 %@ 978-4-86348-720-8

@inproceedings{conf/vlsic/ZimmerVSCFJKKPR19, added-at = {2019-08-06T00:00:00.000+0200}, author = {Zimmer, Brian and Venkatesan, Rangharajan and Shao, Yakun Sophia and Clemons, Jason and Fojtik, Matthew and Jiang, Nan and Keller, Ben and Klinefelter, Alicia and Pinckney, Nathaniel Ross and Raina, Priyanka and Tell, Stephen G. and Zhang, Yanqing and Dally, William J. and Emer, Joel S. and Gray, C. Thomas and Keckler, Stephen W. and Khailany, Brucek}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2087be6156e7d47651f8ed626f38e0bc3/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2019}, ee = {https://doi.org/10.23919/VLSIC.2019.8778056}, interhash = {deac011343bf579af025262539857385}, intrahash = {087be6156e7d47651f8ed626f38e0bc3}, isbn = {978-4-86348-720-8}, keywords = {dblp}, pages = {300-}, publisher = {IEEE}, timestamp = {2019-09-27T16:36:31.000+0200}, title = {A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2019.html#ZimmerVSCFJKKPR19}, year = 2019 }