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A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.

B. Zimmer, R. Venkatesan, Y. Shao, J. Clemons, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina, S. Tell, Y. Zhang, W. Dally, J. Emer, C. Gray, S. Keckler, and B. Khailany. VLSI Circuits, page 300-. IEEE, (2019)

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Sophia Leistner

Sophia Hess University of Stuttgart

Sophia Murr University of Stuttgart

Sophia Gutierrez Beltran University of Stuttgart

Katharina-Sophia Wiegers University of Stuttgart

Other publications of authors with the same name

The Aladdin Approach to Accelerator Design and Modeling.Y. Shao, B. Reagen, G. Wei, and D. Brooks. IEEE Micro, 35 (3): 58-70 (2015)Quantifying acceleration: Power/performance trade-offs of application kernels in hardware.B. Reagen, Y. Shao, G. Wei, and D. Brooks. ISLPED, page 395-400. IEEE, (2013)Hardware Acceleration.M. Kim, and Y. Shao. IEEE Micro, 38 (6): 6-7 (2018)Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis.R. Garibotti, B. Reagen, Y. Shao, G. Wei, and D. Brooks. IEEE Trans. on Circuits and Systems, 65-II (10): 1440-1444 (2018)Timeloop: A Systematic Approach to DNN Accelerator Evaluation.A. Parashar, P. Raina, Y. Shao, Y. Chen, V. Ying, A. Mukkara, R. Venkatesan, B. Khailany, S. Keckler, and J. Emer. ISPASS, page 304-315. IEEE, (2019)Research Infrastructures for Hardware AcceleratorsY. Shao, and D. Brooks. Synthesis Lectures on Computer Architecture Morgan & Claypool Publishers, (2015)NeuroVectorizer: End-to-End Vectorization with Deep Reinforcement Learning.A. Haj-Ali, N. Ahmed, T. Willke, Y. Shao, K. Asanovic, and I. Stoica. CoRR, (2019)ISA-independent workload characterization and its implications for specialized architectures.Y. Shao, and D. Brooks. ISPASS, page 245-255. IEEE Computer Society, (2013)Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures.Y. Shao, B. Reagen, G. Wei, and D. Brooks. ISCA, page 97-108. IEEE Computer Society, (2014)Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures.H. Genc, A. Haj-Ali, V. Iyer, A. Amid, H. Mao, J. Wright, C. Schmidt, J. Zhao, A. Ou, M. Banister and 4 other author(s). CoRR, (2019)

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Disambiguation of "Shao, Yakun Sophia"

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A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.

Please choose a person to relate this publication to

Sophia Leistner

Sophia Hess University of Stuttgart

Sophia Murr University of Stuttgart

Sophia Gutierrez Beltran University of Stuttgart

Katharina-Sophia Wiegers University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Shao, Yakun Sophia"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.

Please choose a person to relate this publication to

Sophia Leistner

Sophia Hess University of Stuttgart

Sophia Murr University of Stuttgart

Sophia Gutierrez Beltran University of Stuttgart

Katharina-Sophia Wiegers University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.