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Disambiguation of "Parashar, Angshuman"

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Timeloop: A Systematic Approach to DNN Accelerator Evaluation.

, , , , , , , , , and . ISPASS, page 304-315. IEEE, (2019)

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Other publications of authors with the same name

Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures., , , , , , , , , and 6 other author(s). ACM Trans. Comput. Syst., 33 (3): 10:1-10:32 (2015)Triggered instructions: a control paradigm for spatially-programmed architectures., , , , , , , , , and 4 other author(s). ISCA, page 142-153. ACM, (2013)A Hierarchical Architectural Framework for Reconfigurable Logic Computing., , , , and . IPDPS Workshops, page 287-292. IEEE, (2013)Leveraging latency-insensitivity to ease multiple FPGA design., , , , , and . FPGA, page 175-184. ACM, (2012)Leap scratchpads: automatic memory and cache management for reconfigurable logic., , , , and . FPGA, page 25-28. ACM, (2011)Timeloop: A Systematic Approach to DNN Accelerator Evaluation., , , , , , , , , and . ISPASS, page 304-315. IEEE, (2019)DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators., , , and . CoRR, (2022)Enabling Flexibility for Sparse Tensor Acceleration via Heterogeneity., , , , , , , and . CoRR, (2022)A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy., , and . ISCA, page 376-386. IEEE Computer Society, (2004)SlicK: slice-based locality exploitation for efficient redundant multithreading., , and . ASPLOS, page 95-105. ACM, (2006)