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Disambiguation of "Krishna, Tushar"

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Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures.

, , , , , , , , , , , , , , , and . ACM Trans. Comput. Syst., 33 (3): 10:1-10:32 (2015)

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Other publications of authors with the same name

Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks., , , , , , and . IEEE Computer, 46 (10): 48-55 (2013)SMART: a single-cycle reconfigurable NoC for SoC applications., , , , , and . DATE, page 338-343. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Single-cycle collective communication over a shared network fabric., and . NOCS, page 1-8. IEEE, (2014)Lightweight Emulation of Virtual Channels using Swaps., and . NoCArc@MICRO, page 1:1-1:6. ACM, (2017)Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures., , , , , , , , , and 6 other author(s). ACM Trans. Comput. Syst., 33 (3): 10:1-10:32 (2015)Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip., , , and . ICRC, page 1-11. IEEE, (2018)FastTrack: Leveraging Heterogeneous FPGA Wires to Design Low-Cost High-Performance Soft NoCs., and . ISCA, page 739-751. IEEE Computer Society, (2018)14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks., , , and . ISSCC, page 262-263. IEEE, (2016)HERALD: Optimizing Heterogeneous DNN Accelerators for Edge Devices., , , and . CoRR, (2019)FastTrack: Exploiting Fast FPGA Wiring for Implementing NoC Shortcuts (Abstract Only)., and . FPGA, page 286. ACM, (2018)