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A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.

B. Zimmer, R. Venkatesan, Y. Shao, J. Clemons, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina, S. Tell, Y. Zhang, W. Dally, J. Emer, C. Gray, S. Keckler, and B. Khailany. VLSI Circuits, page 300-. IEEE, (2019)

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24.1 A 0.6V 8mW 3D vision processor for a navigation device for the visually impaired.D. Jeon, N. Ickes, P. Raina, H. Wang, D. Rus, and A. Chandrakasan. ISSCC, page 416-417. IEEE, (2016)Timeloop: A Systematic Approach to DNN Accelerator Evaluation.A. Parashar, P. Raina, Y. Shao, Y. Chen, V. Ying, A. Mukkara, R. Venkatesan, B. Khailany, S. Keckler, and J. Emer. ISPASS, page 304-315. IEEE, (2019)Reconfigurable processor for energy-scalable computational photography.R. Rithe, P. Raina, N. Ickes, S. Tenneti, and A. Chandrakasan. ISSCC, page 164-165. IEEE, (2013)Correction to "Reconfigurable Processor for Energy-Efficient Computational Photography".R. Rithe, P. Raina, N. Ickes, S. Tenneti, and A. Chandrakasan. J. Solid-State Circuits, 49 (11): 2740 (2014)Reconfigurable Processor for Energy-Efficient Computational Photography.R. Rithe, P. Raina, N. Ickes, S. Tenneti, and A. Chandrakasan. J. Solid-State Circuits, 48 (11): 2908-2919 (2013)An energy-scalable accelerator for blind image deblurring.P. Raina, M. Tikekar, and A. Chandrakasan. ESSCIRC, page 113-116. IEEE, (2016)Automating Vitiligo Skin Lesion Segmentation Using Convolutional Neural Networks.M. Low, and P. Raina. CoRR, (2019)Energy-efficient circuits and systems for computational imaging and vision on mobile devices.P. Raina. Massachusetts Institute of Technology, Cambridge, USA, (2018)ndltd.org (oai:dspace.mit.edu:1721.1/115787).A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.B. Zimmer, R. Venkatesan, Y. Shao, J. Clemons, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina and 7 other author(s). VLSI Circuits, page 300-. IEEE, (2019)A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm.B. Zimmer, R. Venkatesan, Y. Shao, J. Clemons, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina and 7 other author(s). J. Solid-State Circuits, 55 (4): 920-932 (2020)

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A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.

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Disambiguation of "Raina, Priyanka"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.

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A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.