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Disambiguation of "Raina, Priyanka"

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An energy-scalable accelerator for blind image deblurring.

, , and . ESSCIRC, page 113-116. IEEE, (2016)

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Other publications of authors with the same name

Timeloop: A Systematic Approach to DNN Accelerator Evaluation., , , , , , , , , and . ISPASS, page 304-315. IEEE, (2019)24.1 A 0.6V 8mW 3D vision processor for a navigation device for the visually impaired., , , , , and . ISSCC, page 416-417. IEEE, (2016)Correction to "Reconfigurable Processor for Energy-Efficient Computational Photography"., , , , and . J. Solid-State Circuits, 49 (11): 2740 (2014)Reconfigurable processor for energy-scalable computational photography., , , , and . ISSCC, page 164-165. IEEE, (2013)Reconfigurable Processor for Energy-Efficient Computational Photography., , , , and . J. Solid-State Circuits, 48 (11): 2908-2919 (2013)An energy-scalable accelerator for blind image deblurring., , and . ESSCIRC, page 113-116. IEEE, (2016)Energy-efficient circuits and systems for computational imaging and vision on mobile devices.. Massachusetts Institute of Technology, Cambridge, USA, (2018)ndltd.org (oai:dspace.mit.edu:1721.1/115787).A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm., , , , , , , , , and 7 other author(s). VLSI Circuits, page 300-. IEEE, (2019)Automating Vitiligo Skin Lesion Segmentation Using Convolutional Neural Networks., and . CoRR, (2019)A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 55 (4): 920-932 (2020)