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Research Infrastructures for Hardware Accelerators

, and . Synthesis Lectures on Computer Architecture Morgan & Claypool Publishers, (2015)

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The Aladdin Approach to Accelerator Design and Modeling., , , and . IEEE Micro, 35 (3): 58-70 (2015)Quantifying acceleration: Power/performance trade-offs of application kernels in hardware., , , and . ISLPED, page 395-400. IEEE, (2013)Research Infrastructures for Hardware Accelerators, and . Synthesis Lectures on Computer Architecture Morgan & Claypool Publishers, (2015)NeuroVectorizer: End-to-End Vectorization with Deep Reinforcement Learning., , , , , and . CoRR, (2019)Hardware Acceleration., and . IEEE Micro, 38 (6): 6-7 (2018)Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis., , , , and . IEEE Trans. on Circuits and Systems, 65-II (10): 1440-1444 (2018)Timeloop: A Systematic Approach to DNN Accelerator Evaluation., , , , , , , , , and . ISPASS, page 304-315. IEEE, (2019)Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures., , , and . ISCA, page 97-108. IEEE Computer Society, (2014)ISA-independent workload characterization and its implications for specialized architectures., and . ISPASS, page 245-255. IEEE Computer Society, (2013)A modular digital VLSI flow for high-productivity SoC design., , , , , , , , , and 5 other author(s). DAC, page 72:1-72:6. ACM, (2018)