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Disambiguation of "Nedovic, Nikola"

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Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects.

, , , , , , , , , , , , , , , and . CICC, page 1-8. IEEE, (2018)

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Nikola Nezic University of Stuttgart

Nikola Bursac

Ph. D. Nikola Zisi University of Stuttgart

Nikola Mößner University of Stuttgart

Nikola Kovachev University of Stuttgart

 

Other publications of authors with the same name

Timing Characterization of Dual-edge Triggered Flip-flops., , and . ICCD, page 538-541. IEEE Computer Society, (2001)A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers., , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 724-732. Springer, (2005)Conditional pre-charge techniques for power-efficient dual-edge clocking., , and . ISLPED, page 56-59. ACM, (2002)A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2019)Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects., , , , , , , , , and 6 other author(s). CICC, page 1-8. IEEE, (2018)A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 54 (1): 43-54 (2019)A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator., , , , , , , , , and 3 other author(s). ISSCC, page 276-278. IEEE, (2018)A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX., , , , , , , , , and . ISSCC, page 224-598. IEEE, (2007)Comparative analysis of double-edge versus single-edge triggered clocked storage elements., , and . ISCAS (5), page 105-108. IEEE, (2002)Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits., , , and . IEEE Trans. on Circuits and Systems, 55-I (10): 3038-3049 (2008)