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STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process., , , , , , , , and . ESSDERC, page 159-162. IEEE, (2013)Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Technology and architecture for deep submicron RF CMOS technology.. SBCCI, page 4. ACM, (2005)Impact on the back gate degradation in partially depleted SOI n-MOSFETs by 2-MeV electron irradiation., , , , , , , and . Microelectronics Reliability, 46 (9-11): 1731-1735 (2006)Design Technology co-optimization for N10., , , , , , , , , and 18 other author(s). CICC, page 1-8. IEEE, (2014)Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges., , , , and . CICC, page 679-686. IEEE, (2006)Holisitic device exploration for 7nm node., , , , , , , , , and 5 other author(s). CICC, page 1-5. IEEE, (2015)Analysis of microbump induced stress effects in 3D stacked IC technologies., , , , , , , , , and 9 other author(s). 3DIC, page 1-5. IEEE, (2011)Degradation of electrical performance and floating body effect in ultra thin gate oxide FD-SOI n-MOSFETs by 7.5-MeV proton irradiation., , , , , , , and . Microelectronics Reliability, 44 (9-11): 1721-1726 (2004)Identifying the Bottlenecks to the RF Performance of FinFETs., , , , , , and . VLSI Design, page 111-116. IEEE Computer Society, (2010)