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thermo-mechanical behavior of a 3D stack - Challenges and solutions.

G. der Plas, S. Thijs, D. Linten, G. Katti, P. Limaye, A. Mercha, M. Stucchi, H. Oprins, B. Vandevelde, N. Minas, M. Cupac, M. Dehan, M. Nelis, R. Agarwal, W. Dehaene, Y. Travaly, E. Beyne, and P. Marchal. CICC, page 1-4. IEEE, (2010)

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Dr. Michele Nottoli University of Stuttgart

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Global interconnect trade-off for technology over memory modules to application level: case study.A. Papanikolaou, M. Miranda, F. Catthoor, H. Corporaal, H. Man, D. Roest, M. Stucchi, and K. Maex. SLIP, page 125-132. ACM, (2003)Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.G. der Plas, P. Limaye, I. Loi, A. Mercha, H. Oprins, C. Torregiani, S. Thijs, D. Linten, M. Stucchi, G. Katti and 27 other author(s). J. Solid-State Circuits, 46 (1): 293-307 (2011)Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.G. der Plas, S. Thijs, D. Linten, G. Katti, P. Limaye, A. Mercha, M. Stucchi, H. Oprins, B. Vandevelde, N. Minas and 8 other author(s). CICC, page 1-4. IEEE, (2010)Statistically Aware SRAM Memory Array Design.E. Grossar, M. Stucchi, K. Maex, and W. Dehaene. ISQED, page 25-30. IEEE Computer Society, (2006)3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV).J. Olmen, J. Coenen, W. Dehaene, K. Meyer, C. Huyghebaert, A. Jourdain, G. Katti, A. Mercha, M. Rakowski, M. Stucchi and 3 other author(s). 3DIC, page 1-5. IEEE, (2009)Design issues and considerations for low-cost 3D TSV IC technology.G. der Plas, P. Limaye, A. Mercha, H. Oprins, C. Torregiani, S. Thijs, D. Linten, M. Stucchi, G. Katti, D. Velenis and 24 other author(s). ISSCC, page 148-149. IEEE, (2010)Impact of 3D design choices on manufacturing cost.D. Velenis, M. Stucchi, E. Marinissen, B. Swinnen, and E. Beyne. 3DIC, page 1-5. IEEE, (2009)Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits.E. Marinissen, F. Fodor, A. Podpod, M. Stucchi, Y. Jian, and C. Wu. ITC, page 1-10. IEEE, (2018)A tool flow for predicting system level timing failures due to interconnect reliability degradation.J. Guo, A. Papanikolaou, M. Stucchi, K. Croes, Z. Tokei, and F. Catthoor. ACM Great Lakes Symposium on VLSI, page 291-296. ACM, (2008)3D integration: Circuit design, test, and reliability challenges.N. Minas, I. Wolf, E. Marinissen, M. Stucchi, H. Oprins, A. Mercha, G. der Plas, D. Velenis, and P. Marchal. IOLTS, page 217. IEEE Computer Society, (2010)

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Disambiguation of "Stucchi, Michele"

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Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.

Please choose a person to relate this publication to

Dr. Michele Nottoli University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Stucchi, Michele"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.

Please choose a person to relate this publication to

Dr. Michele Nottoli University of Stuttgart

Other publications of authors with the same name

Disambiguation

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history of this post
URL
DOI
BibTeX
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APA
Chicago
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Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.