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s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM.

N. Miura, K. Kasuga, M. Saito, and T. Kuroda. ISSCC, page 436-437. IEEE, (2010)

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MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.S. Saito, Y. Kohama, Y. Sugimori, Y. Hasegawa, H. Matsutani, T. Sano, K. Kasuga, Y. Yoshida, K. Niitsu, N. Miura and 2 other author(s). FPL, page 6-11. IEEE, (2009)3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link.M. Saen, K. Osada, Y. Okuma, K. Niitsu, Y. Shimazaki, Y. Sugimori, Y. Kohama, K. Kasuga, I. Nonomura, N. Irie and 3 other author(s). J. Solid-State Circuits, 45 (4): 856-862 (2010)An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM.K. Niitsu, Y. Shimazaki, Y. Sugimori, Y. Kohama, K. Kasuga, I. Nonomura, M. Saen, S. Komatsu, K. Osada, N. Irie and 3 other author(s). ISSCC, page 480-481. IEEE, (2009)An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM.N. Miura, K. Kasuga, M. Saito, and T. Kuroda. ISSCC, page 436-437. IEEE, (2010)Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration.K. Niitsu, Y. Kohama, Y. Sugimori, K. Kasuga, K. Osada, N. Irie, H. Ishikuro, and T. Kuroda. IEEE Trans. VLSI Syst., 18 (8): 1238-1243 (2010)

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An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM.

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Disambiguation of "Kasuga, Kazutaka"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM.

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An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM.