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MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.

S. Saito, Y. Kohama, Y. Sugimori, Y. Hasegawa, H. Matsutani, T. Sano, K. Kasuga, Y. Yoshida, K. Niitsu, N. Miura, T. Kuroda, and H. Amano. FPL, page 6-11. IEEE, (2009)

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An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor.Y. Hasegawa, S. Abe, H. Matsutani, H. Amano, K. Anjo, and T. Awashima. FPT, page 163-170. IEEE, (2005)Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor.V. Tuan, Y. Hasegawa, and H. Amano. ERSA, page 203-206. CSREA Press, (2007)Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor.Y. Hasegawa, S. Abe, S. Kurotaki, V. Tuan, N. Katsura, T. Nakamura, T. Nishimura, and H. Amano. IPDPS, IEEE, (2006)Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays.Y. Hasegawa, and H. Amano. FPL, page 796-799. IEEE, (2007)Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation.Y. Hasegawa, S. Abe, K. Deguchi, M. Suzuki, and H. Amano. FPGA, page 265. ACM, (2005)Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor.N. Suzuki, S. Kurotaki, M. Suzuki, N. Kaneko, Y. Yamada, K. Deguchi, Y. Hasegawa, H. Amano, K. Anjo, M. Motomura and 3 other author(s). FCCM, page 328-329. IEEE Computer Society, (2004)A cost-effective context memory structure for dynamically reconfigurable processors.M. Suzuki, Y. Hasegawa, V. Tuan, S. Abe, and H. Amano. IPDPS, IEEE, (2006)Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique.Y. Saito, T. Shirai, T. Nakamura, T. Nishimura, Y. Hasegawa, S. Tsutsumi, T. Kashima, M. Nakata, S. Takeda, K. Usami and 1 other author(s). FPT, page 329-332. IEEE, (2008)A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors.H. Amano, Y. Hasegawa, S. Abe, K. Ishikawa, S. Tsutsumi, S. Kurotaki, T. Nakamura, and T. Nishimura. FPL, page 1-6. IEEE, (2006)TCP throughput characteristics over 5G millimeterwave network in indoor train station.M. Okano, Y. Hasegawa, K. Kanai, B. Wei, and J. Katto. WCNC, page 1-6. IEEE, (2019)

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Disambiguation of "Hasegawa, Yohei"

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MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.

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MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.