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MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.

S. Saito, Y. Kohama, Y. Sugimori, Y. Hasegawa, H. Matsutani, T. Sano, K. Kasuga, Y. Yoshida, K. Niitsu, N. Miura, T. Kuroda, and H. Amano. FPL, page 6-11. IEEE, (2009)

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A near-future prediction method for low power consumption on a many-core processor.T. Kodaka, A. Takeda, S. Sasaki, A. Yokosawa, T. Kizu, T. Tokuyoshi, H. Xu, T. Sano, H. Usui, J. Tanabe and 2 other author(s). DATE, page 1058-1059. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors.T. Sano, Y. Saito, and H. Amano. ERSA, page 112-118. CSREA Press, (2009)A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array.Y. Saito, T. Sano, M. Kato, V. Tunbunheng, Y. Yasuda, and H. Amano. ERSA, page 283-286. CSREA Press, (2009)Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors.T. Sano, Y. Saito, M. Kato, and H. Amano. FPL, page 530-533. IEEE, (2009)An evaluation of an energy efficient many-core SoC with parallelized face detection.H. Usui, J. Tanabe, T. Sano, H. Xu, and T. Miyamori. ASP-DAC, page 311-316. IEEE, (2014)MuCCRA-3: a low power dynamically reconfigurable processor array.Y. Saito, T. Sano, M. Kato, V. Tunbunheng, Y. Yasuda, M. Kimura, and H. Amano. ASP-DAC, page 377-378. IEEE, (2010)On Estimation of Tangential Force in Railways Brake Systems by Fuzzy Inference.T. Sano, Y. Endo, S. ichi Nakazawa, and D. Hijikata. JACIII, 19 (5): 639-644 (2015)A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications.H. Xu, J. Tanabe, H. Usui, S. Hosoda, T. Sano, K. Yamamoto, T. Kodaka, N. Nonogaki, N. Ozaki, and T. Miyamori. VLSIC, page 150-151. IEEE, (2012)Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters.T. Miyamori, H. Xu, H. Usui, S. Hosoda, T. Sano, K. Yamamoto, T. Kodaka, N. Nonogaki, N. Ozaki, and J. Tanabe. IEICE Transactions, 97-C (4): 360-368 (2014)Instruction buffer mode for multi-context Dynamically Reconfigurable Processors.T. Sano, M. Kato, S. Tsutsumi, Y. Hasegawa, and H. Amano. FPL, page 215-220. IEEE, (2008)

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MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.

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MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.