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Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors.

T. Sano, Y. Saito, M. Kato, and H. Amano. FPL, page 530-533. IEEE, (2009)

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Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.N. Ozaki, Y. Yasuda, M. Izawa, Y. Saito, D. Ikebuchi, H. Amano, H. Nakamura, K. Usami, M. Namiki, and M. Kondo. IEEE Micro, 31 (6): 6-18 (2011)Geyser-2: The second prototype CPU with fine-grained run-time power gating.L. Zhao, D. Ikebuchi, Y. Saito, M. Kamata, N. Seki, Y. Kojima, H. Amano, S. Koyama, T. Hashida, Y. Umahashi and 7 other author(s). ASP-DAC, page 87-88. IEEE, (2011)Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique.Y. Saito, T. Shirai, T. Nakamura, T. Nishimura, Y. Hasegawa, S. Tsutsumi, T. Kashima, M. Nakata, S. Takeda, K. Usami and 1 other author(s). FPT, page 329-332. IEEE, (2008)Cache Controller Design on Ultra Low Leakage Embedded Processors.L. Zhao, H. Xu, N. Seki, Y. Saito, Y. Hasegawa, K. Usami, and H. Amano. ARCS, volume 5455 of Lecture Notes in Computer Science, page 171-182. Springer, (2009)Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping.K. Hironaka, M. Kimura, Y. Saito, T. Sano, M. Kato, V. Tunbunheng, Y. Yasuda, and H. Amano. FPT, page 349-352. IEEE, (2010)Cool Mega-Array: A highly energy efficient reconfigurable accelerator.N. Ozaki, Y. Yasuda, Y. Saito, D. Ikebuchi, M. Kimura, H. Amano, H. Nakamura, K. Usami, M. Namiki, and M. Kondo. FPT, page 1-8. IEEE, (2011)Power reduction techniques for Dynamically Reconfigurable Processor Arrays.T. Nishimura, K. Hirai, Y. Saito, T. Nakamura, Y. Hasegawa, S. Tsutsumi, V. Tunbunheng, and H. Amano. FPL, page 305-310. IEEE, (2008)Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells.K. Hirai, M. Kato, Y. Saito, and H. Amano. FPT, page 104-111. IEEE Computer Society, (2009)Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors.T. Sano, Y. Saito, M. Kato, and H. Amano. FPL, page 530-533. IEEE, (2009)Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors.T. Sano, Y. Saito, and H. Amano. ERSA, page 112-118. CSREA Press, (2009)

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Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors.

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Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors.