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Disambiguation of "Kodaka, Takeshi"

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Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters.

, , , , , , , , , and . IEICE Transactions, 97-C (4): 360-368 (2014)

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Other publications of authors with the same name

Design and implementation of scalable, transparent threads for multi-core media processor., , , , , , , , , and 3 other author(s). DATE, page 1035-1039. IEEE, (2009)A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 44 (11): 2957-2965 (2009)Development of low power many-core SoC for multimedia applications., , , , , and . DATE, page 773-777. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A novel energy-efficient data acquisition method for wearable devices., , , , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2015)A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications., , , , , , , , , and . VLSIC, page 150-151. IEEE, (2012)Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters., , , , , , , , , and . IEICE Transactions, 97-C (4): 360-368 (2014)Multigrain parallel processing on compiler cooperative chip multiprocessor., , , , , , and . Interaction between Compilers and Computer Architectures, page 11-20. IEEE Computer Society, (2005)A near-future prediction method for low power consumption on a many-core processor., , , , , , , , , and 2 other author(s). DATE, page 1058-1059. EDA Consortium San Jose, CA, USA / ACM DL, (2013)