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Disambiguation of "Kimura, Keiji"

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Multigrain parallel processing on compiler cooperative chip multiprocessor.

, , , , , , and . Interaction between Compilers and Computer Architectures, page 11-20. IEEE Computer Society, (2005)

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Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP., , , , and . International Journal of Parallel Programming, 31 (3): 211-223 (2003)If-Conversion Optimization using Neuro Evolution of Augmenting Topologies., , and . CoRR, (2016)Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding., , , , , , , , , and 5 other author(s). J. Solid-State Circuits, 43 (4): 902-910 (2008)Architecture Design for the Environmental Monitoring System over the Winter Season., , , , , , , and . MobiWac, page 27-34. ACM, (2016)Parallelizing Compiler Translation Validation Using Happens-Before and Task-Set., , , , , and . CANDAR (Workshops), page 87-93. IEEE, (2021)Detection of small cracks in the chain of a trolley conveyor with an infrared camera., , and . J. Intelligent Manufacturing, 4 (4): 259-267 (1993)A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption., , , , , , , , , and 4 other author(s). ISSCC, page 100-590. IEEE, (2007)Power-Aware Compiler Controllable Chip Multiprocessor., , , , and . IEICE Transactions, 91-C (4): 432-439 (2008)A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core., , , , , , , , , and 2 other author(s). IEICE Transactions, 94-C (4): 663-669 (2011)Power-Aware Compiler Controllable Chip Multiprocessor., , , , and . PACT, page 427. IEEE Computer Society, (2007)