%0 Journal Article %1 journals/ieicet/ShikanoSWKK08 %A Shikano, Hiroaki %A Shirako, Jun %A Wada, Yasutaka %A Kimura, Keiji %A Kasahara, Hironori %D 2008 %J IEICE Transactions %K dblp %N 4 %P 432-439 %T Power-Aware Compiler Controllable Chip Multiprocessor. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet91c.html#ShikanoSWKK08 %V 91-C

@article{journals/ieicet/ShikanoSWKK08, added-at = {2018-11-30T00:00:00.000+0100}, author = {Shikano, Hiroaki and Shirako, Jun and Wada, Yasutaka and Kimura, Keiji and Kasahara, Hironori}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/27a5c1ebed6620ff5735587723c33d2b4/dblp}, ee = {https://doi.org/10.1093/ietele/e91-c.4.432}, interhash = {ecde5b0a42809b9a6188ed961226c6c1}, intrahash = {7a5c1ebed6620ff5735587723c33d2b4}, journal = {IEICE Transactions}, keywords = {dblp}, number = 4, pages = {432-439}, timestamp = {2019-09-27T07:16:23.000+0200}, title = {Power-Aware Compiler Controllable Chip Multiprocessor.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet91c.html#ShikanoSWKK08}, volume = {91-C}, year = 2008 }