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Disambiguation of "Wada, Yasutaka"

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Power-Aware Compiler Controllable Chip Multiprocessor.

, , , , and . IEICE Transactions, 91-C (4): 432-439 (2008)

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Other publications of authors with the same name

A Linear-Time and Space Algorithm for Optimal Traffic Signal Durations at an Intersection., , and . CoRR, (2013)A Scalable Multiplier for Arbitrary Large Numbers Supporting Homomorphic Encryption., , and . DSD, page 969-975. IEEE Computer Society, (2013)Software-cooperative power-efficient heterogeneous multi-core for media processing., , , , , , , , , and 1 other author(s). ASP-DAC, page 736-741. IEEE, (2008)A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core., , , , , , , , , and 2 other author(s). IEICE Transactions, 94-C (4): 663-669 (2011)Power-Aware Compiler Controllable Chip Multiprocessor., , , , and . IEICE Transactions, 91-C (4): 432-439 (2008)Power-Aware Compiler Controllable Chip Multiprocessor., , , , and . PACT, page 427. IEEE Computer Society, (2007)Coarse Grain Task Parallelization of Earthquake Simulator GMS Using OSCAR Compiler on Various Cc-NUMA Servers., , , and . LCPC, volume 9519 of Lecture Notes in Computer Science, page 238-253. Springer, (2015)Multigrain parallel processing on compiler cooperative chip multiprocessor., , , , , , and . Interaction between Compilers and Computer Architectures, page 11-20. IEEE Computer Society, (2005)Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing., , , , , , , , , and 2 other author(s). SC, page 78:1-78:12. ACM, (2015)Compiler Control Power Saving Scheme for Multi Core Processors., , , , , and . LCPC, volume 4339 of Lecture Notes in Computer Science, page 362-376. Springer, (2005)