PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Orailoglu, Alex"

Author of the publication

copydeleteadd this publication to your clipboard
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation.

, and . DFT, page 325-333. IEEE Computer Society, (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Charalampos Alexopoulos University of Stuttgart

Univ. -Prof. Dr. rer. pol. Alexander Brem University of Stuttgart

 

Other publications of authors with the same name

Simulated annealing based yield enhancement of layouts., and . Great Lakes Symposium on VLSI, page 166-169. IEEE, (1994)Automatic Synthesis of Self-Recovering VLSI Systems., and . IEEE Trans. Computers, 45 (2): 131-142 (1996)Tracing the best test mix through multi-variate quality tracking., and . VTS, page 1-6. IEEE Computer Society, (2013)Register allocation for simultaneous reduction of energy and peak temperature on registers., , , and . DATE, page 20-25. IEEE, (2011)Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs., , and . DATE, page 865-869. EDA Consortium, San Jose, CA, USA, (2007)Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck?, and . Asian Test Symposium, page 373-378. IEEE Computer Society, (2001)Accumulation-based concurrent fault detection for linear digital state variable systems., and . Asian Test Symposium, page 484-. IEEE Computer Society, (2000)Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection., and . IEEE Trans. VLSI Syst., 20 (12): 2170-2183 (2012)The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations., and . IEEE Trans. Computers, 54 (1): 61-75 (2005)Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs., and . IEEE Trans. Computers, 52 (11): 1480-1489 (2003)