%0 Journal Article %1 journals/expert/HekmatpourOC91 %A Hekmatpour, Amir K. %A Orailoglu, Alex %A Chau, Paul M. %D 1991 %J IEEE Expert %K dblp %N 2 %P 56-70 %T Hierarchical Modeling of the VLSI Design Process. %U http://dblp.uni-trier.de/db/journals/expert/expert6.html#HekmatpourOC91 %V 6

@article{journals/expert/HekmatpourOC91, added-at = {2015-09-09T00:00:00.000+0200}, author = {Hekmatpour, Amir K. and Orailoglu, Alex and Chau, Paul M.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2e085b0c2e8e326723b28c24cbd6595b7/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/64.79710}, interhash = {b4f66af54e29094ca5e27d90d2179419}, intrahash = {e085b0c2e8e326723b28c24cbd6595b7}, journal = {IEEE Expert}, keywords = {dblp}, number = 2, pages = {56-70}, timestamp = {2016-02-02T09:03:43.000+0100}, title = {Hierarchical Modeling of the VLSI Design Process.}, url = {http://dblp.uni-trier.de/db/journals/expert/expert6.html#HekmatpourOC91}, volume = 6, year = 1991 }