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Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection.

, and . IEEE Trans. VLSI Syst., 20 (12): 2170-2183 (2012)

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VDDmin test optimization for overscreening minimization through adaptive scan chain masking., and . VTS, page 313-318. IEEE Computer Society, (2010)On Diagnosis of Timing Failures in Scan Architecture., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (7): 1102-1115 (2012)Scan power reduction in linear test data compression scheme., and . ICCAD, page 78-82. ACM, (2009)Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection., and . IEEE Trans. VLSI Syst., 20 (12): 2170-2183 (2012)Deflecting crosstalk by routing reconsideration through refined signal correlation estimation., and . ACM Great Lakes Symposium on VLSI, page 369-374. ACM, (2009)Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme., and . DATE, page 63-68. IEEE, (2010)Squashing code size in microcoded IPs while delivering high decompression speed., , and . Design Autom. for Emb. Sys., 14 (3): 265-284 (2010)Examining Timing Path Robustness Under Wide-Bandwidth Power Supply Noise Through Multi-Functional-Cycle Delay Test., and . IEEE Trans. VLSI Syst., 22 (4): 734-746 (2014)Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST., , and . IEEE Trans. Computers, 56 (12): 1619-1628 (2007)Scan BIST with biased scan test signals., , and . Science in China Series F: Information Sciences, 51 (7): 881-895 (2008)