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The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations.

, and . IEEE Trans. Computers, 54 (1): 61-75 (2005)

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Highly Configurable Programmable Built-In Self Test Architecture for High-Speed Memories., , and . VTS, page 21-26. IEEE Computer Society, (2005)Microprocessor silicon debug based on failure propagation tracing., , and . ITC, page 10. IEEE Computer Society, (2005)Deterministic partitioning techniques for fault diagnosis in scan-based BIST., and . ITC, page 273-282. IEEE Computer Society, (2000)Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues., , and . ITC, page 1-7. IEEE Computer Society, (2006)Invariance-Based On-Line Test for RTL Controller-Datapath Circuits., , and . VTS, page 459-464. IEEE Computer Society, (2000)ANNSyS: an Analog Neural Network Synthesis System., , , , and . Neural Networks, 12 (2): 325-338 (1999)Low-Cost On-Line Test for Digital Filters., and . VTS, page 446-451. IEEE Computer Society, (1999)Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test., , and . IEEE Trans. Reliability, 53 (2): 269-278 (2004)ANNSyS (an analog neural network synthesis system)., , , , and . ICNN, page 910-915. IEEE, (1997)Concurrent test for digital linear systems., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 20 (9): 1132-1142 (2001)