Author of the publication

Automatic Synthesis of Self-Recovering VLSI Systems.

, and . IEEE Trans. Computers, 45 (2): 131-142 (1996)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection., and . IEEE Trans. VLSI Syst., 20 (12): 2170-2183 (2012)Automatic Synthesis of Self-Recovering VLSI Systems., and . IEEE Trans. Computers, 45 (2): 131-142 (1996)The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations., and . IEEE Trans. Computers, 54 (1): 61-75 (2005)Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs., and . IEEE Trans. Computers, 52 (11): 1480-1489 (2003)Efficient Construction of Aliasing-Free Compaction Circuitry., and . IEEE Micro, 22 (5): 82-92 (2002)Transforming Binary Code for Low-Power Embedded Processors., and . IEEE Micro, 24 (3): 21-33 (2004)Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation., and . DFT, page 325-333. IEEE Computer Society, (2002)Simulated annealing based yield enhancement of layouts., and . Great Lakes Symposium on VLSI, page 166-169. IEEE, (1994)On the identification of modular test requirements for low cost hierarchical test path construction., and . Integration, 40 (3): 315-325 (2007)Tracing the best test mix through multi-variate quality tracking., and . VTS, page 1-6. IEEE Computer Society, (2013)