%0 Conference Paper %1 conf/glvlsi/KarriO94 %A Karri, Ramesh %A Orailoglu, Alex %B Great Lakes Symposium on VLSI %D 1994 %I IEEE %K dblp %P 166-169 %T Simulated annealing based yield enhancement of layouts. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi1994.html#KarriO94 %@ 0-8186-5610-7

@inproceedings{conf/glvlsi/KarriO94, added-at = {2014-09-29T00:00:00.000+0200}, author = {Karri, Ramesh and Orailoglu, Alex}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/28233c76bc9c57a30c203ebb082b36611/dblp}, booktitle = {Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/1994}, ee = {http://dx.doi.org/10.1109/GLSV.1994.289975}, interhash = {abecf4103d57a05751be8931da4c7bf8}, intrahash = {8233c76bc9c57a30c203ebb082b36611}, isbn = {0-8186-5610-7}, keywords = {dblp}, pages = {166-169}, publisher = {IEEE}, timestamp = {2016-02-02T12:49:58.000+0100}, title = {Simulated annealing based yield enhancement of layouts.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi1994.html#KarriO94}, year = 1994 }