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Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAM.

K. Miyaji, Y. Shinozuka, S. Miyano, and K. Takeuchi. CICC, page 1-4. IEEE, (2011)

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Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM.K. Miyaji, Y. Shinozuka, S. Miyano, and K. Takeuchi. IEEE Trans. on Circuits and Systems, 59-I (8): 1635-1643 (2012)A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy.K. Miyaji, T. Suzuki, S. Miyano, and K. Takeuchi. J. Solid-State Circuits, 48 (9): 2239-2249 (2013)A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.M. Terada, S. Yoshimoto, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, and M. Yoshimoto. ISQED, page 489-492. IEEE, (2012)Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress.T. Hiramoto, A. Kumar, T. Saraya, and S. Miyano. IEICE Transactions, 96-C (6): 759-765 (2013)A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges.S. Moriwaki, Y. Yamamoto, A. Kawasumi, T. Suzuki, S. Miyano, T. Sakurai, and H. Shinohara. VLSIC, page 60-61. IEEE, (2012)An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications.M. Kaku, H. Iwai, T. Nagai, M. Wada, A. Suzuki, T. Takai, N. Itoga, T. Miyazaki, T. Iwai, H. Takenaka and 3 other author(s). ISSCC, page 276-277. IEEE, (2008)A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy.K. Miyaji, T. Suzuki, S. Miyano, and K. Takeuchi. ISSCC, page 232-234. IEEE, (2012)0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme.S. Moriwaki, A. Kawasumi, T. Suzuki, T. Sakurai, and S. Miyano. CICC, page 1-4. IEEE, (2011)A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme.S. Yoshimoto, M. Terada, Y. Umeki, S. Okumura, A. Kawasumi, T. Suzuki, S. Moriwaki, S. Miyano, H. Kawaguchi, and M. Yoshimoto. ISLPED, page 85-90. ACM, (2012)A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique.S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, and M. Yoshimoto. IEICE Electronic Express, 9 (12): 1023-1029 (2012)

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAM.

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