%0 Conference Paper %1 conf/vlsic/MoriwakiYKSMSS12 %A Moriwaki, Shinichi %A Yamamoto, Yasuhiro %A Kawasumi, Atsushi %A Suzuki, T. %A Miyano, Shinji %A Sakurai, Takayasu %A Shinohara, Hirofumi %B VLSIC %D 2012 %I IEEE %K dblp %P 60-61 %T A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2012.html#MoriwakiYKSMSS12 %@ 978-1-4673-0848-9

@inproceedings{conf/vlsic/MoriwakiYKSMSS12, added-at = {2016-03-17T00:00:00.000+0100}, author = {Moriwaki, Shinichi and Yamamoto, Yasuhiro and Kawasumi, Atsushi and Suzuki, T. and Miyano, Shinji and Sakurai, Takayasu and Shinohara, Hirofumi}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/23c642f8b0924dd2a2dd6583b40c4d6ca/dblp}, booktitle = {VLSIC}, crossref = {conf/vlsic/2012}, ee = {http://dx.doi.org/10.1109/VLSIC.2012.6243789}, interhash = {3f6830b4cae3d8a8e83eca9e25784d21}, intrahash = {3c642f8b0924dd2a2dd6583b40c4d6ca}, isbn = {978-1-4673-0848-9}, keywords = {dblp}, pages = {60-61}, publisher = {IEEE}, timestamp = {2016-03-18T10:32:32.000+0100}, title = {A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2012.html#MoriwakiYKSMSS12}, year = 2012 }