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A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.

M. Terada, S. Yoshimoto, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, and M. Yoshimoto. ISQED, page 489-492. IEEE, (2012)

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7T SRAM enabling low-energy simultaneous block copy.S. Okumura, S. Yoshimoto, K. Yamaguchi, Y. Nakata, H. Kawaguchi, and M. Yoshimoto. CICC, page 1-4. IEEE, (2010)A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.M. Terada, S. Yoshimoto, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, and M. Yoshimoto. ISQED, page 489-492. IEEE, (2012)A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor.H. Mori, T. Nakagawa, Y. Kitahara, Y. Kawamoto, K. Takagi, S. Yoshimoto, S. Izumi, K. Nii, H. Kawaguchi, and M. Yoshimoto. CICC, page 1-4. IEEE, (2015)A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM.Y. Umeki, K. Yanagida, S. Yoshimoto, S. Izumi, M. Yoshimoto, H. Kawaguchi, K. Tsunoda, and T. Sugii. IPSJ Trans. System LSI Design Methodology, (2016)A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor.H. Mori, Y. Umeki, S. Yoshimoto, S. Izumi, K. Nii, H. Kawaguchi, and M. Yoshimoto. IEICE Transactions, 99-C (8): 901-908 (2016)Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector.S. Izumi, K. Yamashita, M. Nakano, S. Yoshimoto, T. Nakagawa, Y. Nakai, H. Kawaguchi, H. Kimura, K. Marumoto, T. Fuchikami and 4 other author(s). IEEE Trans. Biomed. Circuits and Systems, 9 (5): 641-651 (2015)Flexible electronics for bio-signal monitoring in implantable applications.S. Yoshimoto, T. Araki, T. Uemura, Y. Noda, and T. Sekitani. IEICE Electronic Express, 14 (20): 20172003 (2017)A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems.S. Izumi, K. Yamashita, M. Nakano, T. Nakagawa, Y. Kitahara, K. Yanagida, S. Yoshimoto, H. Kawaguchi, H. Kimura, K. Marumoto and 5 other author(s). BioCAS, page 280-283. IEEE, (2014)A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme.S. Okumura, Y. Iguchi, S. Yoshimoto, H. Fujiwara, H. Noguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto. ISQED, page 659-663. IEEE Computer Society, (2009)A negative-resistance sense amplifier for low-voltage operating STT-MRAM.Y. Umeki, K. Yanagida, S. Yoshimoto, S. Izumi, M. Yoshimoto, H. Kawaguchi, K. Tsunoda, and T. Sugii. ASP-DAC, page 8-9. IEEE, (2015)

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A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.

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A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.