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Disambiguation of "Yoshimoto, Shusuke"

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A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme.

, , , , , , , and . ISQED, page 659-663. IEEE Computer Society, (2009)

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Other publications of authors with the same name

A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction., , , , , , and . ISQED, page 489-492. IEEE, (2012)7T SRAM enabling low-energy simultaneous block copy., , , , , and . CICC, page 1-4. IEEE, (2010)A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor., , , , , , , , , and . CICC, page 1-4. IEEE, (2015)Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector., , , , , , , , , and 4 other author(s). IEEE Trans. Biomed. Circuits and Systems, 9 (5): 641-651 (2015)A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM., , , , , , , and . IPSJ Trans. System LSI Design Methodology, (2016)Flexible electronics for bio-signal monitoring in implantable applications., , , , and . IEICE Electronic Express, 14 (20): 20172003 (2017)A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor., , , , , , and . IEICE Transactions, 99-C (8): 901-908 (2016)A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems., , , , , , , , , and 5 other author(s). BioCAS, page 280-283. IEEE, (2014)A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme., , , , , , , and . ISQED, page 659-663. IEEE Computer Society, (2009)A negative-resistance sense amplifier for low-voltage operating STT-MRAM., , , , , , , and . ASP-DAC, page 8-9. IEEE, (2015)