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A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM.

Y. Umeki, K. Yanagida, S. Yoshimoto, S. Izumi, M. Yoshimoto, H. Kawaguchi, K. Tsunoda, and T. Sugii. IPSJ Trans. System LSI Design Methodology, (2016)

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A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application.Y. Murachi, K. Hamano, T. Matsuno, J. Miyakoshi, M. Miyama, and M. Yoshimoto. IEICE Transactions, 88-A (12): 3492-3499 (2005)The development and impact on business of the world's first live video streaming distribution platform for 3G mobile videophone terminals.H. Ohira, M. Kodama, and M. Yoshimoto. IJEB, 1 (1): 94-105 (2003)A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition.Y. Murachi, Y. Fukuyama, R. Yamamoto, J. Miyakoshi, H. Kawaguchi, H. Ishihara, M. Miyama, Y. Matsuda, and M. Yoshimoto. IEICE Transactions, 91-C (4): 457-464 (2008)Service Interval Optimization with Delay Bound Guarantee for HCCA in IEEE 802.11e WLANs.A. Foronda, Y. Higuchi, C. Ohta, M. Yoshimoto, and Y. Okada. IEICE Transactions, 90-B (11): 3158-3169 (2007)A Real-time Scalable Object Detection System using Low-power HOG Accelerator VLSI.K. Takagi, K. Tanaka, S. Izumi, H. Kawaguchi, and M. Yoshimoto. Signal Processing Systems, 76 (3): 261-274 (2014)A 40-NM 54-MW 3×-real-time VLSI processor for 60-kWord continuous speech recognition.G. He, Y. Miyamoto, K. Matsuda, S. Izumi, H. Kawaguchi, and M. Yoshimoto. SiPS, page 147-152. IEEE, (2013)An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding.K. Mizuno, J. Miyakoshi, Y. Murachi, M. Hamamoto, T. Iinuma, T. Ishihara, F. Yin, J. Lee, H. Kawaguchi, and M. Yoshimoto. ICECS, page 1179-1182. IEEE, (2008)A 40-nm 144-mW VLSI processor for real-time 60-kWord continuous speech recognition.G. He, T. Sugahara, T. Fujinaga, Y. Miyamoto, H. Noguchi, S. Izumi, H. Kawaguchi, and M. Yoshimoto. ASP-DAC, page 71-72. IEEE, (2013)A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition.G. He, T. Sugahara, T. Fujinaga, Y. Miyamoto, H. Noguchi, S. Izumi, H. Kawaguchi, and M. Yoshimoto. CICC, page 1-4. IEEE, (2011)Impact of Aggregation Efficiency on GIT Routing forWireless Sensor Networks.T. Aonishi, T. Matsuda, S. Mikami, H. Kawaguchi, C. Ohta, and M. Yoshimoto. ICPP Workshops, page 151-158. IEEE Computer Society, (2006)

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A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM.

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A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM.