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readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor.

H. Mori, T. Nakagawa, Y. Kitahara, Y. Kawamoto, K. Takagi, S. Yoshimoto, S. Izumi, K. Nii, H. Kawaguchi, and M. Yoshimoto. CICC, page 1-4. IEEE, (2015)

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Advanced memory topics.K. Nii, and T. Kirihata. CICC, page 1. IEEE, (2013)Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration.H. Shinohara, K. Nii, and H. Onodera. IEICE Transactions, 91-C (9): 1488-1500 (2008)A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor.H. Mori, T. Nakagawa, Y. Kitahara, Y. Kawamoto, K. Takagi, S. Yoshimoto, S. Izumi, K. Nii, H. Kawaguchi, and M. Yoshimoto. CICC, page 1-4. IEEE, (2015)A 6.05-Mb/mm2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time.M. Yabuuchi, Y. Sawada, T. Sano, Y. Ishii, S. Tanaka, M. Tanaka, and K. Nii. VLSI Circuits, page 1-2. IEEE, (2016)Automotive low power technology for IoT society.T. Yamauchi, H. Kondo, and K. Nii. VLSIC, page 80-. IEEE, (2015)A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure.M. Yabuuchi, H. Fujiwara, Y. Tsukamoto, M. Tanaka, S. Tanaka, and K. Nii. CICC, page 1-4. IEEE, (2013)Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential.H. Noguchi, Y. Iguchi, H. Fujiwara, S. Okumura, K. Nii, H. Kawaguchi, and M. Yoshimoto. IPSJ Trans. System LSI Design Methodology, (2011)A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations.K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, H. Makino, Y. Yamagami, S. Ishikura, T. Terano, T. Oashi and 6 other author(s). J. Solid-State Circuits, 43 (1): 180-191 (2008)A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die.S. Ohbayashi, M. Yabuuchi, K. Kono, Y. Oda, S. Imaoka, K. Usui, T. Yonezu, T. Iwamoto, K. Nii, Y. Tsukamoto and 8 other author(s). J. Solid-State Circuits, 43 (1): 96-108 (2008)A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.Y. Nakata, Y. Kimi, S. Okumura, J. Jung, T. Sawada, T. Toshikawa, M. Nagata, H. Nakano, M. Yabuuchi, H. Fujiwara and 4 other author(s). IEICE Transactions, 97-C (4): 332-341 (2014)

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A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor.

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A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor.