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Disambiguation of "Ohbayashi, Shigeki"

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A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die.

, , , , , , , , , , , , , , , , , and . J. Solid-State Circuits, 43 (1): 96-108 (2008)

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Other publications of authors with the same name

A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology., , , , , , , , , and 11 other author(s). IEICE Transactions, 91-C (8): 1338-1347 (2008)Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access., , , , , , , , and . J. Solid-State Circuits, 44 (3): 977-986 (2009)A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations., , , , , , , , , and 6 other author(s). J. Solid-State Circuits, 43 (1): 180-191 (2008)A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die., , , , , , , , , and 8 other author(s). J. Solid-State Circuits, 43 (1): 96-108 (2008)A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations., , , , , , , , , and 6 other author(s). ISSCC, page 326-606. IEEE, (2007)A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die., , , , , , , , , and 7 other author(s). ISSCC, page 488-617. IEEE, (2007)A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 43 (4): 938-945 (2008)A yield improvement methodology based on logic redundant repair with a repairable scan flip-flop designed by push rule., , , and . ISQED, page 184-190. IEEE, (2010)A Yield and Reliability Improvement Methodology Based on Logic Redundant Repair with a Repairable Scan Flip-Flop Designed by Push Rule., , , , , and . ACM Trans. Design Autom. Electr. Syst., 17 (2): 17:1-17:22 (2012)Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability., , , , , , , , and . ICCAD, page 398-405. IEEE Computer Society, (2005)