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Disambiguation of "Tsukamoto, Yasumasa"

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A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations.

, , , , , , , , , , , , , , , and . J. Solid-State Circuits, 43 (1): 180-191 (2008)

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Other publications of authors with the same name

A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure., , , , , and . CICC, page 1-4. IEEE, (2013)A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die., , , , , , , , , and 8 other author(s). J. Solid-State Circuits, 43 (1): 96-108 (2008)A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations., , , , , , , , , and 6 other author(s). J. Solid-State Circuits, 43 (1): 180-191 (2008)A dynamic body-biased SRAM with asymmetric halo implant MOSFETs., , , , , , and . ISLPED, page 285-290. IEEE/ACM, (2011)A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues., , , , , , and . J. Solid-State Circuits, 46 (11): 2535-2544 (2011)Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application., , , , , and . ISQED, page 270-274. IEEE, (2012)A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs., , , , , , , and . ISSCC, page 236-238. IEEE, (2012)1.8 Mbit/mm2 ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology., , , , and . VLSIC, page 274-. IEEE, (2015)Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs., , , , , , , and . CICC, page 1-4. IEEE, (2011)A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias., , , , , and . ISSCC, page 356-357. IEEE, (2010)