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A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.

Y. Nakata, Y. Kimi, S. Okumura, J. Jung, T. Sawada, T. Toshikawa, M. Nagata, H. Nakano, M. Yabuuchi, H. Fujiwara, K. Nii, H. Kawai, H. Kawaguchi, and M. Yoshimoto. IEICE Transactions, 97-C (4): 332-341 (2014)

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A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.Y. Nakata, Y. Kimi, S. Okumura, J. Jung, T. Sawada, T. Toshikawa, M. Nagata, H. Nakano, M. Yabuuchi, H. Fujiwara and 4 other author(s). ISQED, page 16-23. IEEE, (2014)Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path.G. Matsukawa, Y. Kimi, S. Yoshida, S. Izumi, H. Kawaguchi, and M. Yoshimoto. IEICE Transactions, 99-A (6): 1198-1205 (2016)Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path.Y. Kimi, G. Matsukawa, S. Yoshida, S. Izumi, H. Kawaguchi, and M. Yoshimoto. ATS, page 139-144. IEEE Computer Society, (2015)An accurate soft error propagation analysis technique considering temporal masking disablement.Y. Kimi, G. Matsukawa, S. Yoshida, S. Izumi, H. Kawaguchi, and M. Yoshimoto. IOLTS, page 23-25. IEEE, (2015)A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM.G. Matsukawa, Y. Nakata, Y. Kimi, Y. Sugure, M. Shimozawa, S. Oho, H. Kawaguchi, and M. Yoshimoto. ARCS Workshops, page 1-5. VDE Verlag / IEEE Xplore, (2014)A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme.G. Matsukawa, Y. Nakata, Y. Sugure, S. Oho, Y. Kimi, M. Shimozawa, S. Yoshida, H. Kawaguchi, and M. Yoshimoto. IEICE Transactions, 98-C (4): 333-339 (2015)A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.Y. Nakata, Y. Kimi, S. Okumura, J. Jung, T. Sawada, T. Toshikawa, M. Nagata, H. Nakano, M. Yabuuchi, H. Fujiwara and 4 other author(s). IEICE Transactions, 97-C (4): 332-341 (2014)

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A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.

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A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.