Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

X-masking during logic BIST and its impact on defect coverage.

Y. Tang, H. Wunderlich, P. Engelke, I. Polian, B. Becker, J. Schlöffel, F. Hapke, and M. Wittke. IEEE Trans. VLSI Syst., 14 (2): 193-202 (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Patrick Pietrantuono University of Stuttgart

Other publications of authors with the same name

TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.A. Czutro, I. Polian, M. Lewis, P. Engelke, S. Reddy, and B. Becker. VLSI Design, page 227-232. IEEE Computer Society, (2009)Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.I. Polian, S. Kundu, J. Gallière, P. Engelke, M. Renovell, and B. Becker. VTS, page 343-348. IEEE Computer Society, (2005)Simulating Resistive-Bridging and Stuck-At Faults.P. Engelke, I. Polian, M. Renovell, and B. Becker. IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (10): 2181-2192 (2006)SUPERB: Simulator utilizing parallel evaluation of resistive bridges.P. Engelke, B. Becker, M. Renovell, J. Schlöffel, B. Braitling, and I. Polian. ACM Trans. Design Autom. Electr. Syst., 14 (4): 56:1-56:21 (2009)Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis.A. Czutro, I. Polian, M. Lewis, P. Engelke, S. Reddy, and B. Becker. International Journal of Parallel Programming, 38 (3-4): 185-202 (2010)An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.N. Houarche, M. Comte, M. Renovell, A. Czutro, P. Engelke, I. Polian, and B. Becker. VTS, page 21-26. IEEE Computer Society, (2009)X-Masking During Logic BIST and Its Impact on Defect Coverage.Y. Tang, H. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, and B. Becker. ITC, page 442-451. IEEE Computer Society, (2004)A Simulator of Small-Delay Faults Caused by Resistive-Open Defects.A. Czutro, N. Houarche, P. Engelke, I. Polian, M. Comte, M. Renovell, and B. Becker. European Test Symposium, page 113-118. IEEE Computer Society, (2008)The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.P. Engelke, I. Polian, M. Renovell, B. Seshadri, and B. Becker. VTS, page 171-178. IEEE Computer Society, (2004)Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics.I. Polian, P. Engelke, and B. Becker. ISMVL, page 216-223. IEEE Computer Society, (2002)

PUMA

Disambiguation of "Engelke, Piet"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

X-masking during logic BIST and its impact on defect coverage.

Please choose a person to relate this publication to

Patrick Pietrantuono University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Engelke, Piet"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML X-masking during logic BIST and its impact on defect coverage.

Please choose a person to relate this publication to

Patrick Pietrantuono University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

X-masking during logic BIST and its impact on defect coverage.